Yuxuan Zhang

I'm a software engineer at Google.

I received my PhD from Computer & Information Science Department of University of Pennsylvania, where my advisor is Prof. Sebastian Angel, and my former advisor is Prof. Joseph Devietti.

I'm broadly interested in bridging the gap between data center applications and server processors by an intersection of techniques in OS, compilers and hardware.

Education

• PhD in Computer Science, University of Pennsylvania (GPA: 4.0)
• MS in Electrical Engineering, University of Michigan, Ann Arbor [...]
  • Two-way superscalar R10K Out-of-Order processor
    
    • Implemented 2-way associate non-blocking writeback data cache and its cache controller which maintains outstanding cache misses status.
    • Implemented key components such as Reservation Station, hardware register map table, Reorder Buffer, Load Store Queue of the OoO processor.
    • Modified visual debugging tools and re-design the testbench to support performance analysis of the OoO processor.
  • Design and Verify a Cache Coherency Protocol
    
    • Designed and verified an invalidation based MOESI self-downgrade cache coherence protocol for the multicore memory system by enumerative model checker Murphi.
  • Wikipedia Search Engine
    
    • Built a scalable search engine which supports information retrieval based on both tf-idf and PageRank scores.
    • Indexed webpages with Hadoop MapReduce framework to scale to large corpus sizes.
    • Built a new search engine interface with two special features: user-driven scoring and summarization.
• BS in Electrical Engineering, Harbin Institute of Technology

Publications

• Quilt: Resource-aware Merging of Serverless Workflows
  [paper] [code] [slides]
  Y. Zhang, S. Angel
  Proc. ACM Symposium on Operating Systems Principles (SOSP), Oct. 2025
• RPG2: Robust Profile-Guided Runtime Prefetch Generation
  [paper] [code] [slides] [poster]
  Y. Zhang, N. Sobotka, S. Park, S. Jamilan, T. A. Khan, B. Kasikci, G. Pokam, H. Litz, J. Devietti
  Proc. International Conf. on Architectural Support for Programming Languages and Operating Systems (ASPLOS), May. 2024.
• Online COde Layout OptimizationS via Ocolos
  [paper]
  Y. Zhang, T. A. Khan, G. Pokam, B. Kasikci, H. Litz, J. Devietti.
  IEEE Micro "Top Picks From the 2022 Computer Architecture Conferences", May. 2023.
• OCOLOS: Online COde Layout OptimizationS
  [paper] [code] [slides]
  Y. Zhang, T. A. Khan, G. Pokam, B. Kasikci, H. Litz, J. Devietti.
  Proc. International Symposium on Microarchitecture (MICRO), Oct. 2022.

Employment

• Software Engineer, Google LLC.
• Software Engineer Intern, Google LLC. [...]
  • Technical Infrastructure Development Team, Sunnyvale, CA, 05.2025 - 08.2025
  • AI Agent for BigQuery Benchmark Generation
  • Analyze performance bottlenecks in Google’s production workloads via profile collected by Google-Wide Profiling (GWP).
  • Use LLM tool AlphaEvolve to generate synthetic workloads which yields the same performance metrics as production workloads
• Software Engineer Intern, VMware LLC. [...]
  • Monitor Team, Boston, MA, 05.2022 - 08.2022
  • Prevalidation during Pre-copy of memory pages
  • Offloaded the pre-validation of the destination VM’s page table from Virtual Machine Monitor(VMM) to ESXi (VMKernel, the hypervisor) after a VM is migrated from source to destination (VMotion), in order to reduce the contention of updating page tables on different VMs.
  • Built prevalidation during the pre-copy of memory pages in VMotion to reduce the time spending on pre-validation.
• Research Intern, Microsoft Research Asia [...]
  • Network Research Group, Beijing, China, 01.2018 - 07.2019
  • GLane on GPU
  • Built a Linux module that exposes an Nvidia GPU’s physical memory for direct data transfer, and a hardware stack for GPUs in a device-centric cluster to buffer and transfer data.
  • Prototyped CUDA code to perform GPU computation and data transfer in parallel without host CPU involvement.
• Software Engineer Intern, Nvidia Corp. [...]
  • High Performance Computing team, Beijing, China, 05.2017 - 09.2017
  • Input Batching for TensorRT
  • Developed a CPU-side input batching framework for TensorRT to optimize data flow for deep learning inference workloads.
  • Implemented dynamic dispatching logic that buffers inputs until a specific throughput threshold is met, ensuring optimal batch sizes before GPU transfer.
  • Enhanced overall GPU throughput by reducing the frequency of host-to-device memory copies and optimizing processing efficiency.

Honor & Awards

• Paper selected for IEEE Micro Top Picks in Computer Architecture from 2023
• Outstanding Graduates Awards
  Awarded by Harbin Institute of Technology for overall academic excellence at graduation
• Fuji Xerox Scholarship
  Awarded for ranking 1st in undergraduate GPA for one academic year
• Suzhou Industrial Park Scholarship
  Awarded for ranking 2nd in undergraduate GPA for one academic year

Talks

• RPG2: Robust Profile-Guided Runtime Prefetch Generation.
  ASPLOS, San Diego, CA, May 2024
• OCOLOS: Online Code Layout OptimizationS.
  MICRO, Chicago, IL, Oct. 2022

Professional Service

• Journal reviewer for IEEE Transactions on Computers (TOC), 2023

---

Miscellaneous

• I enjoy writing fan fictions, and my self-published fan fictions have been sold more than 1,100 copies in China.
• I studied Japanese in the UPenn’s Japanese Language Program. I’ve passed the JLPT N3, and am aiming to pass the N2.
• I had been learning Chinese dance for 7 years and playing the piano for 5 years, and received certificates from Beijing Dance Academy and Central Conservatory of Music.